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? semiconductor components industries, llc, 2002 june, 2002 rev. 2 1 publication order number: nlast4052/d nlast4052 analog multiplexer/ demultiplexer ttl compatible, doublepole, 4position plus common off the nlast4052 is an improved version of the mc14052 and mc74hc4052 fabricated in submicron silicon gate cmos technology for lower r ds(on) resistance and improved linearity with low current. this device may be operated either with a single supply or dual supply up to 3 v to pass a 6 v pp signal without coupling capacitors. when operating in single supply mode, it is only necessary to tie v ee , pin 7 to ground. for dual supply operation, v ee is tied to a negative voltage, not to exceed maximum ratings. translation is provided in the device, the address and inhibit pins are standard ttl level compatible. for cmos compatibility see nlas4052. pin for pin compatible with all industry standard versions of `4052.' ? improved r ds(on) specifications ? pin for pin replacement for max4052 and max4052a one half the resistance operating at 5.0 volts ? single or dual supply operation single 35 volt operation, or dual 3 volt operation with v cc of 3.0 to 3.3 v, device can interface with 1.8 v logic, no translators needed address and inhibit pins are logic is overvoltage tolerant and may be driven up +6 v regardless of v cc ? address and inhibit pins are standard ttl compatible greatly improved noise margin over max4052 and max4052a true ttl compatibility v il = 0.8 v, v ih = 2.0 v ? improved linearity over standard hc4052 devices ? popular soic, and space saving tssop, and qsop 16 pin packages so16 d suffix case 751b tssop16 dt suffix case 948f 1 8 9 16 nlast4052 awlyww marking diagrams nlast alyw a = assembly location l, wl = wafer lot y = year w = work week ordering information device package shipping nlast4052d so16 48 units/rail nlast4052dr2 so16 2500 units/reel NLAST4052DT tssop16 96 units/rail NLAST4052DTr2 tssop16 2500 units/reel nlast4052qs qsop16 98 units/rail nlast4052qsr qsop16 2500 units/reel qsop16 qs suffix case 492 nlast 4052 alyw 18 16 9 18 16 9 http://onsemi.com
nlast4052 http://onsemi.com 2 figure 1. pin connection (top view) figure 2. logic diagram 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 no 1a no 2a com a no 0a no 3a add b add a no 0b no 1b com b no 3b no 2b inhibit v ee gnd com a no 2a no 3a inhibit no 0b add b no 0a no 1a no 1b com b no 3b no 2b add a logic truth table address inhibit b a on switches* 1 x don't care x don't care all switches open 0 0 0 com a no 0a , com b no 0b 0 0 1 com a no 1a , com b no 1b 0 1 0 com a no 2a , com b no 2b 0 1 1 com a no 3a , com b no 3b 0 0 0 com a no 0a , com b no 0b 0 0 1 com a no 1a , com b no 1b 0 1 0 com a no 2a , com b no 2b 0 1 1 com a no 3a , com b no 3b *n/c, no, and com pins are identical and interchangeable. either may be considered an input or output; signals pass equally well in either direction.
nlast4052 http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? maximum ratings (note 1) ????? ????? symbol ????????????????????? ????????????????????? parameter ??????? ??????? value ??? ??? unit ????? ????? v ee ????????????????????? ????????????????????? negative dc supply voltage (referenced to gnd) ??????? ??????? 7.0 to 0.5 ??? ??? v ????? ????? v cc ????????????????????? ????????????????????? positive dc supply voltage (note 2) (referenced to gnd) (referenced to v ee ) ??????? ??????? 0.5 to 7.0 0.5 to 7.0 ??? ??? v ????? ????? v is ????????????????????? ????????????????????? analog input voltage ??????? ??????? v ee 0.5 to v cc 0.5 ??? ??? v ????? ????? v in ????????????????????? ????????????????????? digital input voltage (referenced to gnd) ??????? ??????? 0.5 to 7.0 ??? ??? v ????? ????? i ????????????????????? ????????????????????? dc current, into or out of any pin ??????? ??????? 50 ??? ??? ma ????? ????? t stg ????????????????????? ????????????????????? storage temperature range ??????? ??????? 65 to 150 ??? ??? c ????? ????? t l ????????????????????? ????????????????????? lead temperature, 1 mm from case for 10 seconds ??????? ??????? 260 ??? ??? c ????? ????? t j ????????????????????? ????????????????????? junction temperature under bias ??????? ??????? 150 ??? ??? c ????? ? ??? ? ????? ja ????????????????????? ? ??????????????????? ? ????????????????????? thermal resistance soic tssop qsop ??????? ? ????? ? ??????? 143 164 164 ??? ? ? ? ??? c/w ????? ? ??? ? ????? p d ????????????????????? ? ??????????????????? ? ????????????????????? power dissipation in still air, soic tssop qsop ??????? ? ????? ? ??????? 500 450 450 ??? ? ? ? ??? mw ????? ????? msl ????????????????????? ????????????????????? moisture sensitivity ??????? ??????? level 1 ??? ??? ????? ????? f r ????????????????????? ????????????????????? flammability rating oxygen index: 30% 35% ??????? ??????? ul 94 v0 @ 0.125 in ??? ??? ????? ? ??? ? ? ??? ? ????? v esd ????????????????????? ? ??????????????????? ? ? ??????????????????? ? ????????????????????? esd withstand voltage human body model (note 3) machine model (note 4) charged device model (note 5) ??????? ? ????? ? ? ????? ? ??????? 2000 200 1000 ??? ? ? ? ? ? ? ??? v ????? ????? i latchup ????????????????????? ????????????????????? latchup performance above v cc and below gnd at 125 c (note 6) ??????? ??????? 300 ??? ??? ma 1. absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. 2. the absolute value of v cc |v ee | 7.0. 3. tested to eia/jesd22a114a. 4. tested to eia/jesd22a115a. 5. tested to jesd22c101a. 6. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit ???? ???? v ee ?????????????????????? ?????????????????????? negative dc supply voltage (referenced to gnd) ???? ???? 5.5 ???? ???? gnd ??? ??? v ???? ? ?? ? ???? v cc ?????????????????????? ? ???????????????????? ? ?????????????????????? positive dc supply voltage (referenced to gnd) (referenced to v ee ) ???? ? ?? ? ???? 2.5 2.5 ???? ? ?? ? ???? 5.5 6.6 ??? ? ? ? ??? v ???? ???? v is ?????????????????????? ?????????????????????? analog input voltage ???? ???? v ee ???? ???? v cc ??? ??? v ???? ???? v in ?????????????????????? ?????????????????????? digital input voltage (note 7) (referenced to gnd) ???? ???? 0 ???? ???? 5.5 ??? ??? v ???? ???? t a ?????????????????????? ?????????????????????? operating temperature range, all package types ???? ???? 55 ???? ???? 125 ??? ??? c ???? ???? t r , t f ?????????????????????? ?????????????????????? input rise/fall time v cc = 3.0 v 0.3 v (channel select or enable inputs) v cc = 5.0 v 0.5 v ???? ???? 0 0 ???? ???? 100 20 ??? ??? ns/v 7. unused digital inputs may not be left open. all digital inputs must be tied to a highlogic voltage level or a lowlogic inpu t voltage level.
nlast4052 http://onsemi.com 4 dc characteristics digital section (voltages referenced to gnd) v cc guaranteed limit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage, address or inhibit inputs 3.0 4.5 5.5 1.6 2.0 2.0 1.6 2.0 2.0 1.6 2.0 2.0 v v il maximum lowlevel input voltage, address or inhibit inputs 3.0 4.5 5.5 0.5 0.8 0.8 0.5 0.8 0.8 0.5 0.8 0.8 v i in maximum input leakage current, address or inhibit inputs v in = 6.0 or gnd 0 v to 6.0 v 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) address, inhibit, and v is = v cc or gnd 6.0 4.0 40 80 a dc electrical characteristics analog section ???? ???? ???????? ???????? ?????????? ?????????? ?? ?? v cc ??? ??? v ee ?????????? ?????????? guaranteed limit ?? ?? ???? ???? symbol ???????? ???????? parameter ?????????? ?????????? test conditions ?? ?? v cc v ??? ??? v ee v ????? ????? 55 to 25 c ??? ??? 85 c ???? ???? 125 c ?? ?? unit ???? ? ?? ? ? ?? ? ???? r on ???????? ? ?????? ? ? ?????? ? ???????? maximum aono resistance ?????????? ? ???????? ? ? ???????? ? ?????????? v in = v il or v ih v is = v ee to v cc |i s | = 10 ma (figures 4 thru 9) ?? ?? ?? ?? 3.0 4.5 3.0 ??? ? ? ? ? ? ? ??? 0 0 3.0 ????? ? ??? ? ? ??? ? ????? 86 37 26 ??? ? ? ? ? ? ? ??? 108 46 33 ???? ? ?? ? ? ?? ? ???? 120 55 37 ?? ?? ?? ?? ???? ? ?? ? ???? r on ???????? ? ?????? ? ???????? maximum difference in aono resistance between any two channels in the same package ?????????? ? ???????? ? ?????????? v in = v il or v ih, v is = 2.0 v v is = 3.5 v |i s | = 10 ma, v is = 2.0 v ?? ?? ?? 3.0 4.5 3.0 ??? ? ? ? ??? 0 0 3.0 ????? ? ??? ? ????? 15 13 10 ??? ? ? ? ??? 20 18 15 ???? ? ?? ? ???? 20 18 15 ?? ?? ?? r flat(on) on resistance flatness v com 1, 2, 3.5 v v com 2, 0, 2 v 4.5 3.0 3.0 4 2 4 2 5 3 i nc(off) i no(off) maximum offchannel leakage current switch off v in = v il or v ih v io = v cc 1.0 v or v ee +1.0 v (figure 17) 6.0 3.0 0 3.0 0.1 0.1 5.0 5.0 100 100 na i com(on) maximum onchannel leakage current, channel tochannel switch on v io = v cc 1.0 v or v ee +1.0 v (figure 17) 6.0 3.0 0 3.0 0.1 0.1 5.0 5.0 100 100 na
nlast4052 http://onsemi.com 5 ac characteristics (input t r = t f = 3 ns) ???? ???? ????????? ????????? ???????? ???????? ?? ?? ??? ??? ??????????? ??????????? guaranteed limit ?? ?? ???? ???? ????????? ????????? ???????? ???????? ?? ?? v cc ??? ??? v ee ?????? ?????? 55 to 25 c ??? ??? ???? ???? ?? ?? ???? ???? symbol ????????? ????????? parameter ???????? ???????? test conditions ?? ?? v cc v ??? ??? v ee v ??? ??? min ???? ???? typ* ??? ??? 85 c ???? ???? 125 c ?? ?? unit t bbm minimum breakbeforemake time v in = v il or v ih v is = v cc r l = 300 c l = 35 pf (figure 19) 3.0 4.5 3.0 0.0 0.0 3.0 1.0 1.0 1.0 6.5 5.0 3.5 ns *typical characteristics are at 25 c. ac characteristics (c l = 50 pf, input t r = t f = 3 ns) guaranteed limit v cc v ee 55 to 25 c 85 c 125 c symbol parameter v cc v v ee v min typ max min max min max unit t trans transition time (address selection time) (figure 18) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t on turnon time (figures 14, 15, 20, and 21) enable to n o or n c 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t off turnoff time (figures 14, 15, 20, and 21) enable to n o or n c 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns typical @ 25 c, v cc = 5.0 v c in maximum input capacitance,select inputs 8 pf c no or c nc analog i/o 10 c com common i/o 10 c (on) feedthrough 1.0
nlast4052 http://onsemi.com 6 additional application characteristics (gnd = 0 v) v cc v ee typ symbol parameter condition v cc v v ee v 25 c unit bw maximum onchannel bandwidth or minimum frequency response v is = ? (v cc v ee ) source amplitude = 0 dbm (figures 10 and 22) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 110 130 140 140 mhz v iso offchannel feedthrough isolation f = 100 khz; v is = ? (v cc v ee ) source = 0 dbm (figures 12 and 22) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 93 93 93 93 db v onl maximum feedthrough on loss v is = ? (v cc v ee ) source = 0 dbm (figures 10 and 22) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 2 2 2 2 db q charge injection v in = v cc to v ee, f is = 1 khz, t r = t f = 3 ns r is = 0 , c l = 1000 pf, q = c l * v out (figures 16 and 23) 5.0 3.0 0.0 3.0 9.0 12 pc thd total harmonic distortion thd + noise f is = 1 mhz, r l = 10 k , c l = 50 pf, v is = 5.0 v pp sine wave v is = 6.0 v pp sine wave (figure 13) 6.0 3.0 0.0 3.0 0.10 0.05 %
nlast4052 http://onsemi.com 7 v is (vdc) temperature ( c) figure 3. i cc versus temp, v cc = 3 v and 5 v i cc (na) 40 60 80 20 0 100 20 120 v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 4. r on versus v cc , temp = 25 c figure 5. typical on resistance v cc = 2.0 v, v ee = 0 v figure 6. typical on resistance v cc = 3.0 v, v ee = 0 v figure 7. typical on resistance v cc = 4.5 v, v ee = 0 v figure 8. typical on resistance v cc = 5.5 v, v ee = 0 v 4.0 4.0 6.0 2.0 0 2.0 80 60 40 100 20 0 r on ( ) 2.0 v 3.0 v 4.5 v 3.3 v 5.5 v 0 10 20 30 40 50 0 0.5 1.0 1.5 2.0 2.5 3. 0 125 c 85 c 25 c 55 c vcom (v) r on ( ) 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0 vcom (v) r on ( ) 0 5 10 15 25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 125 c 85 c 25 c 55 c 55 c 125 c 85 c 25 c vcom (v) r on ( ) 20 vcom (v) 40 30 20 50 10 r on ( ) 0 2.0 1.5 1.0 0.5 125 c 85 c 25 c 55 c 90 80 70 100 60
nlast4052 http://onsemi.com 8 figure 9. typical on resistance v cc = 3.3 v, v ee = 3.3 v figure 10. bandwidth 10 frequency (mhz) off isolation 10 db/div 0 0.1 10 1.0 100 20 30 40 50 60 70 80 90 100 10 1000 100 10000 0 0.1 0.01 frequency (mhz) distortion (%) 10000 4.5 3.0 3.3 5.5 figure 11. phase shift 0.1 10 1.0 100 frequency (mhz) phase shift (deg) 90 phase shift 54 18 18 54 90 figure 12. off isolation fi g ure 13. total harmonic distortion 72 36 0 36 72 125 c 85 c 25 c 55 c 0 5 10 15 20 4 2 0 2 4 vcom (v) r on ( ) 25 10 0.1 10 1.0 100 frequency (mhz) bandwidth (db) 0 bandwidth (onresponse) 20 30 40 50 50 40 30 20 10
nlast4052 http://onsemi.com 9 3.0 30 2.5 4.5 35 figure 14. t on and t off versus v cc v cc (volts) figure 15. t on and t off versus temp temperature ( c) time (ns) time (ns) figure 16. charge injection versus com voltage v com (v) q (pc) 55 25 125 40 20 15 25 0 034 2 15 t on v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 0.5 10 5 t off t on (ns) t off (ns) v cc = 4.5 v 3.5 4 30 20 15 25 0 10 5 85 55 20 leakage (na) figure 17. switch leakage versus temperature 1 i no(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100 t a = 25 c
nlast4052 http://onsemi.com 10 90% 90% 50% 50% output input 0 v 35 pf enable input open dut output 90% gnd output gnd input 35 pf output address select pin dut 50% 50% 90% 10% 0 v output input 35 pf output address select pin figure 18. channel selection propagation delay 300 v cc v cc 0.1 f v out v ee v ee v cc 300 v cc v cc 90% of v oh t on t off v oh v cc 0.1 f t bmm v out gnd v cc 300 v out 0.1 f figure 19. t bbm (time breakbeforemake) figure 20. t on /t off t trans t trans
nlast4052 http://onsemi.com 11 transmitted output input reference dut 50% 50% 10% 10% 0 v input output 35 pf output enable input open dut channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl 50 50 generator 50 v out v in v out v in v cc t on t off v cc 300 v out v cc v ol figure 21. t on /t off figure 22. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl
nlast4052 http://onsemi.com 12 off on off output open dut v out v cc gnd v in c l figure 23. charge injection: (q) v in output typical operation 8 7 16 +3.0 v 8 7 16 +5.0 v figure 24. 5.0 volts single supply v cc = 5.0 v, v ee = 0 figure 25. dual supply v cc = 3.0 v, v ee = 3.0 v 3.0 v v cc v cc v ee gnd v ee gnd
nlast4052 http://onsemi.com 13 package dimensions soic16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
nlast4052 http://onsemi.com 14 package dimensions tssop16 dt suffix case 948f01 issue o ?? ?? ?? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n
nlast4052 http://onsemi.com 15 package dimensions qsop16 qs suffix case 49201 issue o max millimeters g r b a l m 0.25 (0.010) t u t seating plane k d 16 pl c m 0.25 (0.010) t ba s s v n j m f 8 pl detail e detail e h x 45 rad. mold pin dim min max min inches a 4.80 4.98 0.189 0.196 b 3.81 3.99 0.150 0.157 c 1.55 1.73 0.061 0.068 d 0.20 0.31 0.008 0.012 f 0.41 0.89 0.016 0.035 g 0.64 bsc 0.025 bsc h 0.20 0.46 0.008 0.018 j 0.249 0.191 0.0098 0.0075 k 0.10 0.25 0.004 0.010 l 5.84 6.20 0.230 0.244 m 0 8 0 8 n 0 7 0 7 p 0.18 0.28 0.007 0.011 q 0.51 dia 0.020 dia r 0.64 0.89 0.025 0.035 u 0.64 0.89 0.025 0.035 v notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. the bottom package shall be bigger than the top package by 4 mils (note: lead side only). bottom package dimension shall follow the dimension stated in this drawing. 4. plastic dimensions does not include mold flash or protrusions. mold flash or protrusions shall not exceed 6 mils per side. 5. bottom ejector pin will include the country of origin (coo) and mold cavity i.d. 0 8 0 8 mark q p 0.013 x 0.005 dp. max rad. 0.0050.010 typ
nlast4052 http://onsemi.com 16 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nlast4052/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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